Rapid Formal Verification as Requirements Stage Verification and Validation Technique

Abstract

Early formal verification of a system during initial stages of development has the potential to improve the confidence in the system specifications, in addition to improving the formal verifiability throughout the software development cycle. A formal verification methodology is derived to achieve system modelling and verification during the requirements specification and system design phase. This is achieved by using Focus Stream theory for developing a formal system model derived from requirements analysis leading to a preliminary software design. This results into component architecture and it incorporates the development of component behaviour using Finite Sate Machines. The models developed for real time system encompass modelling of infinite state domains. After model development, formal property enumeration under various categories is done. An enhanced safety property verification is proposed and implemented using Linear Temporal Logic propositions, pattern based properties and system safety based property patterns. Properties verification on the model is done in order to validate and refine the specifications. Derived properties are verified using NuXMV Satisfiability Modulo Theories based algorithms. Tool verification as mandated in RTCA DO-330 is incorporated in the proposed methodology. The proposed approach is practical, implementable by system designers and scalable to handle industrial systems.