Abstract
Design Space Exploration (DSE) is an indispensable segment of the High Level Synthesis (HLS) design process. Moreover, the enormous increase in complexity of the recent Very Large Scale Integration (VLSI) circuits has only been possible due to use of advan ced DSE techniquesduring HLS process. This dissertation presents four automated optimization algorithms and methodologies that are capable to handle various multi-objective problems during design space exploration and high level synthesis of computation intensive applications. Algorithmic solutions to four different branches of DSE problems have been proposed in this dissertation viz. a) Solution to power-performance-area/cost trade-off of Digital Signal Processing (DSP) kernels using priority factor process which also includes deriving analytical mathematical model for modern performance parametric frameworks b) Solution to area-performance-power tradeoff/ power-performance-area tradeoff of DSP kernels using hybridization of fuzzy algorithm and vector design space technique with Self-Correction Scheme c) Solution to dual parametric optimization using efficient multi structure genetic algorithm for integrated scheduling and allocation and d) Solution to control step bound static power optimization using power gradient methodology for integrated scheduling and allocation. Some techniques proposed are equipped with pipelined execution time parameter (based on need), in addition to hardware area, power and cost depending on the user’s objective for exploration of a final solution in a short time. In addition to architecture exploration capability, rapid automated circuit generation of DSP kernels is also possible in a short time for verification and synthesis in Field Programmable Gate Array (FPGA) platforms. The proposed exploration approaches are applied to custom data intensive applications application specific processors/custom processors) or standalone Application Specific Integrated Circuits (ASIC’s). Results of the experiments for proposed approaches on all the standard DSP benchmarks have indicated improvements either in terms of exploration runtime, quality of final solution, reduced execution time, power and area or a multiple combination of all factors when compared to recent approaches.
Highlights
The never ending increase in the growth of chip complexity has only been possible due to efficient scheduling and exploration techniques
This chapter describes the complete experimental results of the four proposed algorithms/methodologies which resolves four branches of the design space exploration problem: a) Design Space Exploration methodology for Power-Performance-Cost/Area tradeoff in High Level Synthesis using novel Priority Factor approach b) Design Space Exploration methodology for Hardware Area-Performance-power tradeoff in High Level Synthesis using Hybrid Fuzzified approach c) Methodology for Integrated exploration of Scheduling and Module Allocation in High Level Synthesis for static power optimization under minimum control step based on Power Gradient theory d) Methodology for Integrated Exploration of Scheduling and Module Allocation in High Level Synthesis for Power-Performance tradeoff using Heuristic Genetic
The dissertation introduced four different frameworks for performing fast and efficient multi-objective tradeoff based on different user criteria viz. a) Novel Priority Factor based Pareto optimal framework methodology for accelerated design space exploration based on power-performance-area/cost tradeoff
Summary
Dissertation Submitted By: Anirban Sengupta, Doctor of Philosophy, 2013 Electrical and Computer Engineering Department, Ryerson University, Canada. Design Space Exploration (DSE) is an indispensable segment of the High Level Synthesis (HLS) design process. This dissertation presents four automated optimization algorithms and methodologies that are capable to handle various multi-objective problems during design space exploration and high level synthesis of computation intensive applications. Some techniques proposed are equipped with pipelined execution time parameter (based on need), in addition to hardware area, power and cost depending on the user’s objective for exploration of a final solution in a short time. Results of the experiments for proposed approaches on all the standard DSP benchmarks have indicated improvements either in terms of exploration runtime, quality of final solution, reduced execution time, power and area or a multiple combination of all factors when compared to recent approaches
Sign-in/Register to view highlights & summary Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
