Abstract
Evaluating different architectures is an important step in implementing signal processing algorithms in hardware. Often specific resource or memory requirements and performance can be estimated only through simulation. This can be difficult when detailed system descriptions are used. There is a need for quick simulation and estimation of performance. The Rapid Abstract Control (RAC) model is presented as an approach to solve this problem. Simple primitives are defined that can be used to construct models for simulation. The Single Scale Retinex (SSR) algorithm is used to demonstrate the effectiveness of the modeling approach.
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