Abstract
In this paper, we review the phenomenology of random telegraph noise (RTN) in 3D NAND Flash arrays. The main features of such arrays resulting from their mainstream integration scheme are first discussed, pointing out the relevant role played by the polycrystalline nature of the string silicon channels on current transport. Starting from that, experimental data for RTN in 3D arrays are presented and explained via theoretical and simulation models. The attention is drawn, in particular, to the changes in the RTN dependences on the array working conditions that resulted from the transition from planar to 3D architectures. Such changes are explained by considering the impact of highly-defective grain boundaries on percolative current transport in cell channels in combination with the localized nature of the RTN traps.
Highlights
Random telegraph noise (RTN) in MOS transistors has been an important topic of interest in the solid-state device community since the 80s, when results of low-frequency noise characterization [1] showed a transition from a typical 1/ f behavior at high temperatures to a series of discrete switching events as temperature was lowered
The physical picture accepted that accounts for such results is based on the fact that, in scaled devices, dopants must be viewed as individual ions rather than a continuous distribution, resulting in randomly-placed charges in the depletion region
“Macaroni” MOSFET, and is the result of clever device engineering in 3D NAND: after the vertical high-aspect ratio holes have been etched in the structure of Figure 1, and the blocking, storage and tunnel layers deposited, the remaining part of the cylinder must be filled with silicon
Summary
Random telegraph noise (RTN) in MOS transistors has been an important topic of interest in the solid-state device community since the 80s, when results of low-frequency noise characterization [1] showed a transition from a typical 1/ f behavior at high temperatures to a series of discrete switching events as temperature was lowered. Moving from early investigations and models [4,5,6,7,8,9], the RTN picture grew more complex, as novel time and amplitude observations [10,11,12,13,14] hinted at a non-negligible role played by non-uniform electron conduction in submicron devices [15,16] This idea gained traction when the phenomenon began to be investigated in Flash memories [17,18,19,20,21,22,23], demonstrating current fluctuations up to 60% [22] and threshold voltage (VT ) shifts reaching 700 mV [18] in 90-nm technology node devices. We will focus our attention on the main experimental data presented in the literature, taking advantage of the model results to provide interpretation for them
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