RAMON: Region-Aware Memory Controller

Abstract

Recent implementations of heterogeneous multicore systems [central processing unit (CPU), graphics processing unit (GPU), and hybrid] address the issue of communication latency between CPU and GPU memory systems by merging these two, so that they can share the same memory address space. In recent years, the combination of the escalation in the number of cores with the rise in memory-intensive applications has significantly increased bandwidth (Bw) needs in both homogeneous and heterogeneous systems. Since tasks assigned to CPU and/or GPU cores will have different Bw demands, a two-tier memory system is needed. Hence, in this paper, Region-Aware Memory cONtroller (RAMON) is proposed as a configurable memory system where different address space regions are able to be dedicated to a different number of memory controllers (MCs), concurrently to supply different amounts of Bw to a different number of cores, providing different levels of memory parallelism. By having different address space regions—simply regions, each with a different number of MCs to match its Bw needs, memory interference per region is reduced. Our findings show that RAMON is promising and improves Bw by a factor of 9 times for CPU regions, 14.1 times for GPU regions, and 4.5 times for combined heterogeneous regions.