Raised-Source/Drain Double-Gate Transistor Design Optimization for Low Operating Power

Abstract

In this simulation-based study, the raised-source/drain (RSD) double-gate MOSFET design is optimized for scaling to gate lengths below 10 nm, and its performance is compared against that of the dopant-segregated Schottky (DSS) double-gate MOSFET design, for applications requiring low operating power. It is found that the RSD design provides for higher drive current and shorter intrinsic delay than the DSS design, for the same total device length (<; 30 nm). Thus, the use of RSD regions is the preferred approach to lower parasitic resistance for deeply scaled double-gate MOSFETs.