Radiation-Hardened Designs for Soft-Error-Rate Reduction by Delay-Adjustable D-Flip-Flops

Abstract

For reducing soft error rate (SER) in system-level failures, this paper proposes a radiation-hardened design by Delay-Adjustable D Flip-Flop (DAD-FF), which can be generally applied to sequential circuits such as shift registers. DAD-FF, modified from the Built-In Soft-Error Resilience (BISER) latch, can be easily integrated in the CAD flow and its delay can be adjusted to reject particle strikes with the maximum energy level. As a result, at the device level, DAD-FF eliminates 99.999997% soft errors by heavy ions on a satellite orbiting at a height of 720 km, and shows greater reduction on SER (e.g. 1.3E10X in the best case) than the standard DFF (STD-FF) through TCAD and SPICE simulation. Moreover, a real chip was also fabricated in a CMOS 90nm technology and performed the experiment of radiation exposure in UCL, Belgium. The laboratory measurement indicates that at the system level, the radiation-hardened design by DAD-FFs achieves 15.69X and 2.62X improvements on the overall SER, compared with those by STD-FFs and DICEs, respectively.