Radiation Tolerance of Devices and Circuits in a 3D Technology Based on the Vertical Integration of Two 130-nm CMOS Layers

Abstract

Total ionizing dose effects are studied in 130-nm transistors and pixel sensors in a vertically integrated two-layer CMOS technology, evaluating the possible impact of 3D integration on radiation tolerance and damage mechanisms. Measurements of static characteristics and noise voltage spectra before and after exposure to high total ionizing doses demonstrate that the analog performance of transistors as well as their radiation hardness are not degraded by mechanical and thermal stresses occurring during the fabrication of the 3D chips. The paper also presents irradiation results on 3D CMOS pixel sensors with a sparsified readout architecture. After exposure to ionizing radiation, these devices behave in a very similar way as analogous counterparts in a standard 2D 130-nm process, confirming that performance advantages associated with 3D integration are not impaired by an enhanced radiation sensitivity.