Abstract
With the construction of the Large Hadron Collider at the European Center for Nuclear Research (CERN), the radiation levels at large High Energy Physics (HEP) experiments are significantly increased with respect to past experience. The approach the HEP community is using to ensure radiation tolerance of the electronics installed in these new generation experiments is described. Particular attention is devoted to developments that led to original work: the estimate of the SEU rate in the complex LHC radiation environment and the use of hardness by design techniques to achieve radiation hardness of ASICs in a commercial CMOS technology.
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