Radiation hardness trends in new microelectronic technologies for the readout of semiconductor detectors

Abstract

The semiconductor detector community is taking advantage of the most recent developments in the field of microelectronics for the design of high performance readout chips. Commercial CMOS foundries are progressing towards an aggressive scaling of the device feature size; 3D integration of two or more CMOS layers might provide an alternative or additional way to increase functional density and improve the performance of the detector system. On the other hand, advanced applications of semiconductor detectors in high energy physics, photon science and space experiments require that sensors and front-end electronics stand high levels of radiation. This paper reviews the main mechanisms that influence the radiation tolerance of nanoscale CMOS devices. This provides the basis for a discussion of the impact of radiation hardness criteria on the design and technology choices for microelectronic chips in new semiconductor detector systems.