Racetrack Memory based hybrid Look-Up Table (LUT) for low power reconfigurable computing

Abstract

The large area and high power consumption are the two main bottlenecks in the conventional SRAM-based Field Programmable Gate Arrays (FPGAs). In recent works, resistive Non-Volatile Memories (NVMs) have been widely proposed to tackle the above issues in the reconfigurable computing systems, due to their non-volatility, fast read/write speed and high-density. The magnetic Domain-Wall (DW) Racetrack Memory (RM) is the emerging NVM with the great prospect of the development of the low-power and high-density circuits and systems. This paper presents RM based single-context and multi-context hybrid Look-Up Tables (LUTs). The hybrid structure allows the LUT to support both volatile input (low-power and high-speed input) and non-volatile input. The non-volatile input is used to reduce the leakage power and also to provide additional reusable resources to increase the hardware utilization. Compared to the SRAM-based 6-input LUT, the proposed non-volatile LUT reduces the number of transistors and leakage power by 80.2% and 84.2%, respectively. The proposed design also reduces the leakage power of the conventional 6-input non-volatile LUT by 17.4% with 27.3% fewer transistors and 36% faster operation speed. The Verilog-to-Routing (VTR) simulation results show that the proposed 6-input LUT consumes 27.1% less power than the SRAM-based counterpart. It may also provide 15.2% additional reusable resource. The context of the proposed multi-context LUT can be switched in 4 ns with the context switching energy of 397.24 fJ/LUT.