Race Logic: Abusing Hardware Race Conditions to Perform Useful Computation

Abstract

This article proposes a novel computing approach, dubbed race logic, in which information, instead of being represented as logic levels (as in conventional logic), is represented as a timing delay. Under this new representation, computations are based on the observation of the relative propagation times of signals injected into the circuit (that is, the outcome of races). Race logic is especially suited for solving problems related to the traversal of directed acyclic graphs commonly used in dynamic programming algorithms. The main advantage of this novel approach is that information processing (min-max and addition operations) can be efficiently expressed through the manipulation of the natural delay chaining inherent to digital designs, which then results in superior latency, throughput, and energy efficiency. To verify this hypothesis, the authors designed several race logic implementations of a DNA global sequence alignment engine and compared them to a state-of-the-art conventional systolic array implementation. The synthesized design shows that synchronous race logic is up to 4x faster when both approaches are mapped to 0.5-micron CMOS standard cell technology. At the same time, the throughput for sequence matching per circuit area is about 3x higher at 5x lower power density for 20-long-symbol DNA sequences.