Abstract
Even high stuck-at fault coverage manufacturing test programs cannot assure high quality for CMOS VLSI circuits. Measurement of quiescent power supply current Iddq) is a means of improving quality and reliability by detecting many defects that do not have appropriate representation in the stuck-at fault model. Since each Iddq measurement takes significant time, a hierarchical fault analysis methodology is proposed for selecting a small subset of production test vectors for I DDQ measurements. A software system QUIETEST has been developed on the basis of this methodology. For two VLSI circuits QUIETEST selected less than 1% of production test vectors for covering all modeled faults that would have been covered by I DDQ measurement for ail of the vectors. The fault models include leakage faults and weak faults for representing defects such as gate oxide shorts and certain opens.
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