Quantum error mitigation by hidden inverses protocol in superconducting quantum devices * * This manuscript has been authored by UT-Battelle, LLC, under Contract No. DE-AC0500OR22725 with the U.S. Department of Energy. The United States Government retains and the publisher, by accepting the article for publication, acknowledges that the United States Government retains a non-exclusive, paid-up, irrevocable, world-wide license to publish

Abstract

We present a method to improve the convergence of variational algorithms based on hidden inverses (HIs) to mitigate coherent errors. In the context of error mitigation, this means replacing the hardware implementation of certain Hermitian gates with their inverses. Doing so results in noise cancellation and a more resilient quantum circuit. This approach improves performance in a variety of two-qubit error models where the noise operator also inverts with the gate inversion. We apply the mitigation scheme on superconducting quantum processors running the variational quantum eigensolver (VQE) algorithm to find the H ground-state energy. When implemented on superconducting hardware we find that the mitigation scheme effectively reduces the energy fluctuations in the parameter learning path in VQE, reducing the number of iterations for a converged value. We also provide a detailed numerical simulation of VQE performance under different noise models and explore how HIs and randomized compiling affect the underlying loss landscape of the learning problem. These simulations help explain our experimental hardware outcomes, helping to connect lower-level gate performance to application-specific behavior in contrast to metrics like fidelity which often do not provide an intuitive insight into observed high level performance.