Quantum Dot Channel (QDC) FETs with Wraparound II–VI Gate Insulators: Numerical Simulations

Abstract

This paper presents simulations predicting the feasibility of 9-nm wraparound quantum dot channel (QDC) field-effect transistors (FETs). In particular, II–VI lattice-matched layers which reduce the density of interface states, serving as top (tunnel gate), side, and bottom gate insulators, have been simulated. Quantum simulations show FET operation with voltage swing of ~0.2 V. Incorporation of cladded quantum dots, such as SiOx–Si and GeOx–Ge, under the gate tunnel oxide results in electrical transport in one or more quantum dot layers which form a quantum dot superlattice (QDSL). Long-channel QDC FETs have experimental multistate drain current (ID)–gate voltage (VG) and drain current (ID)–drain voltage (VD) characteristics, which can be attributed to the manifestation of extremely narrow energy minibands formed in the QDSL. An approach for modeling the multistate ID–VG characteristics is reported. The multistate characteristics of QDC FETs permit design of compact two-bit multivalued logic circuits.