Abstract
Three-dimensional (3D) integration is the most promising technology to improve IC performance by stacking some active device layers and connecting them using vertical interconnections. In this paper, in order to quantitatively evaluate the benefits of 3D IC, wire length distributions in 3D ICs are derived by adapting the simulated quenching algorithm for 3D placement and routing of specific benchmark circuits. By evaluating the wire length distribution, we can confirm that the total wire length is reduced by 26.0 and 41.3% with three and five active layers, respectively. Similarly, 38.1 and 52.0% reduction in the longest wire length with three and five active layers can be achieved.
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