Abstract
We present a new approach for early analysis of logic gates that is based on formal methods. As device technology research takes years and is very expensive, it is desirable to evaluate a technology’s potential as early as possible, which is hard to do with current techniques. The actual impact of new devices on circuit design and their performance in complex circuits, are difficult to predict using simulation-based techniques. We propose a new approach that supplements simulation-based analysis and enables the development of standard cells alongside ongoing fundamental device research. Thereby, it potentially shortens the development cycle and time to market of a new technology. We develop a new discrete charge-transport model for electrical networks and a new flexible model of polarity-reconfigurable transistors as our formal basis. These models make circuit designs accessible to an analysis using probabilistic model checking and power our experiments. Besides worst-case analysis, we leverage measures hardly accessible to simulation such as average delay and average energy consumption per switching operation. We complement this with an automated design-space exploration that yields all reasonable implementations of a switching function built with reconfigurable transistors. After demonstrating the accuracy of our approach by comparison with finite element method analysis results, we undergo a comprehensive design-space exploration and analysis of the 3-minority function. The quantitative results are ranked with respect to various performance metrics, and we analyze the most promising circuit implementations in detail to derive a design guide that yields the best implementation for given statistics of the input patterns.
Highlights
Device technologies with enhanced functionality or advantageous physical properties over established CMOS devices are in research with the goal to supplement or even replace current technologies
As we demonstrate in this work, the toolset relies on very little device data that might come from finite element method (FEM) analysis or early measurements
As the delays turned out to be linear in H we can make the load a second parameter of the obtained rational functions straightforwardly by calculating a circuit variants slope in H. These results demonstrate that a detailed circuit analysis uncovers the potential of reconfigurable transistors and allows us to pick the optimal solution for the targeted application scenario
Summary
Device technologies with enhanced functionality or advantageous physical properties over established CMOS devices are in research with the goal to supplement or even replace current technologies. Though, each transistor has enhanced functionality that directly influences circuit design and characteristics These influences should be investigated as early as possible as the insights might feedback on the development of the emerging device itself. Both start with fundamental device research at TRL 1–2 and mostly rely on the finite element method (FEM) [10], [11] to simulate the device and obtain insights into its basic properties. In contrast to simulation methods like SPICE [12], we do not rely on detailed compact or table models which are hardly available at earlier TRLs. Our approach improves on the current development flow by parallelizing the design of standard cells (D1) with the device research. The developed tools, all models, and raw experimental data are available here: https://cfaed.tu-dresden.de/pd-downloads
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