Abstract
A plan-view analytical method to detect nano-voids of deposited copper layers, especially for the fabrication of printed circuit boards, was investigated using transmission electron microscopy (TEM). Through electroless plating, thin copper layers were directly deposited on small silicon nitride window grids, and the presence of nano-voids within the deposited copper layers were confirmed with various TEM analytical techniques. The amount and size of the nano-voids were further quantified from the plan-view TEM images, making it possible to compare quickly multiple samples prepared under various plating conditions. This analytical method is practical as it is faster in detecting and measuring nano-scale defects when compared to typical cross-sectional analytical methods.
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