Quality-of-service and error control techniques for network-on-chip architectures

Abstract

Networks-on-a-Chip (NoC) has been proposed as a solution for addressing the design challenges of future high-performance nanoscale architectures. Real-time applications require multiple service levels to account for traffic with low delay jitter. As technology scales toward deep submicron, on-chip interconnects are becoming more and more sensitive to noise sources such as power supply noise, crosstalk, radiation induced effects, that are likely to reduce the reliability of data. This paper addresses two important aspects of NoC architecture, QoS (Quality of Service) and Error Control and makes the following contributions: (i) It presents techniques for supporting guaranteed throughput and best-effort traffic quality levels in NoC router, (ii) It provides models for integrating error control schemes in the NoC router architecture, and (iii) It presents cycle accurate power and performance models of the two architecture enhancements for a 4x4 mesh based NoC architecture.