Abstract
AbstractFaults based on complex logic phenomena such as bridges, opens, and delays are increasing as microfabrication progresses and chips speeds increase. However, the capacity for detecting such faults with merely a test set, which has the goal of reducing the number of test patterns based on conventional single stuck‐at fault models, is not sufficient. This paper offers a multifaceted evaluation of the fault detection capacity of a logic BIST using pseudorandom patterns, based on the idea that the detection of such faults will be possible through the generation of combinations of diverse logic values with many test patterns. Through fault simulation for several fault models and the evaluation of a logic BIST using real devices, it is shown that it is possible to detect faults which could not be detected with a conventional scan test set. © 2006 Wiley Periodicals, Inc. Electron Comm Jpn Pt 2, 89(12): 63–70, 2006; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/ecjb.20323
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