Qualitative analysis and deadlock prevention of a real-world IC wafer fabrication system

Abstract

The etching area of a real-world IC wafer fabrication system located in Taiwan's Hsinchu Science-Based Industrial Park can be modeled using Petri net modules. In this paper, the system model, where a single global buffer is assumed, is analyzed for important qualitative properties in manufacturing: boundedness, liveness, and a property slightly weaker than reversibility called almost reversibility. It is proven that the system net is bounded. The net is live and almost reversible if the number of global buffer rooms is not smaller than the maximal number of wafers processed in the etching area (or WIP). This condition is satisfied in the target system since (1) the global buffer rooms are flexible, and (2) the usual WIP in the area is about half the monthly system throughput. This results in a simple deadlock prevention policy for the target area.