Qualification approaches and thermal cycle test results for CSP/BGA/FCBGA

Abstract

Qualification of newly developed multifunctional electronic packages, e.g. system in a package (SIP), are becoming complex at the package level and even more at the assembly and system levels. After many years of data collection, just recently industry agreed to release an industry-wide specification for single die area array package assembly qualification. Probability risk assessment, being implemented by NASA for space flight missions, may be narrowed at the element level for advanced electronic systems and SIP, and further narrowed at the electronic subsystem level. This paper will review the key elements of an industry-wide specification recently published by the IPC (association connecting electronics industries). It will report on a few other unique qualification approaches that are currently being either implemented or developed for risk reduction in high reliability applications. Risk level assessment based 2-P, 3-P, and LogNormal distributions will be compared for plastic ball grid array (PBGA) and flip chip BGA (FCBGA). For this case, risks are compared using cycles-to-failures (CTFs) test results for temperature ranges of −30 to 100 °C and 0 to 100 °C (two profiles). In addition, CTFs up to 1,500 cycles in the range of −55 to 125 °C for a 784 I/O FCBGA (flip chip BGA, a 175 I/O FPBGA (fine pitch BGA)), and a 313 I/O PBGA (plastic BGA) are compared. Inspection results along with scanning electron microscopy and optical cross-sectional photos revealing damage and failure mechanisms are also included.