Abstract

AbstractThis article proposes a new technique for designing multi‐phase voltage controlled oscillators (VCOs), which were implemented in the standard TSMC 0.35 μm SiGe 3P3M BiCMOS process. The quadrature voltage‐controlled oscillator (QVCO) consists of two direct‐ injection locked frequency dividers (ILFDs) with a tail MOSFET. The 2nd harmonic frequency component at the drain node of tail transistor in one ILFD is injected to the gate of injection MOSFET in the other ILFD to couple the two independent ILFDs. The eight‐phase VCO is also designed with similar technique to couple four differential VCOs. At the supply voltage of 3.0 V, the output phase noise of the QVCO is −118.22 dBc/Hz at 1 MHz offset frequency from the carrier frequency of 2.28 GHz, and the figure of merit is −173.25 dBc/Hz. At the supply voltage of 3.0 V, the total power consumption is 14.4 mW. At the supply voltage of 3.0 V, the output phase noise of the eight‐phase VCO is −116.14 dBc/Hz at 1 MHz offset frequency from the carrier frequency of 2.92 GHz, and the figure of merit is −171.3 dBc/Hz. © 2008 Wiley Periodicals, Inc. Microwave Opt Technol Lett 51: 395–398, 2009; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.24053

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