QRL: A High Performance Quadruple-Rail Logic for Resisting DPA on FPGA Implementations

Abstract

Dual-Rail Precharge Logic (DPL) has proven to be an effective countermeasure logic style against Differential Power Analysis (DPA). All previous DPL architectures employ the precharge mechanism to achieve DPA resistance. However, due to its additional precharge phase, an inherent drawback of these DPL architectures lies within its degraded performance (less than 1/2 times compared to the nominal data rate), and hence they are not suitable for applications where high performance is required. In this paper, we present Quadruple-Rail Logic (QRL), a new DPA-hardened approach for cryptographic implementations in FPGA. The main merit of this proposal is that the system throughput can be effectively maintained by removing the precharge phase. By introducing a synchronized and identical quadruple-rail network, strengthened DPA resistance can be achieved. In order to test the robustness of QRL against DPA, we launch DPA on a QRL-based standard AES processor on Xilinx Virtex-5 FPGA. The experimental results show that DPA on QRL AES is failed by analyzing 100,000 power consumption traces, which achieves the competitive DPA resistance level as typical DPL schemes, and gains at least 110 times stronger than the unprotected AES.