Abstract

QR decomposition (QRD) is one of the performance bottlenecks of transceiver processor in the multiuser multiple-input-multiple-output (MU-MIMO) systems. This paper proposes a QRD algorithm based on the existing modified Gram-Schmidt (MGS) algorithm and iteration look-ahead MGS (ILMGS) algorithm, which is named modified ILMGS (MILMGS) algorithm. A corresponding hardware architecture based on the proposed MILMGS algorithm is designed in 0.13 \(\upmu \)m CMOS technique to decompose the \(4\times 4\) real matrix. The implementation results show that the gate count of the designed hardware architecture is 250.2 K, the throughput and the critical path are 95.2 M/s and 3.5 ns respectively.

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