Abstract
The QRD LS algorithm is generally recognised for its superior numerical properties under finite-precision implementation. Furthermore, its systolic architecture is well suited for VLSI implementation. In DFE applications the inherent and implementation nonlinearities make it impossible to analyse precisely all effects of finite-precision arithmetic. The paper presents finite precision results of a QRD LS DFE using the TMS320C25 16-bit precision DSP processors as a simulation platform. Using the bit error rate as a performance measure, results are presented for 2-PSK, 4-PSK and Pi/4-DQPSK modulation formats. Also presented are the numerical accuracy and convergence sensitivity for the filter weights. These results may serve as a basis for practical implementation of QRD LS DFEs.
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