QEC: A Logical Equivalence Checking Framework Targeting SFQ Superconducting Circuits

Abstract

Superconducting devices have emerged as one of the most promising beyond-CMOS technologies with a switching delay of 1ps and switching energy of 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-19</sup> J to achieve high performance, energy-efficient systems and make quantum computing a reality. Design and verification methodologies of single flux quantum (SFQ) logic fundamentally differ from those of the CMOS logic, due to key differences such as pulse signal type, ultra-deep (gate-level) pipelining, and path-balancing in SFQ circuits. In this paper, we propose a framework for logical equivalence checking (LEC) of SFQ circuits called qEC. qEC is built on the ABC tool however with the ability to check on properties of SFQ superconducting circuits. Several timing and structural checks are embedded in our framework. We benchmark the framework on post-synthesis netlists with an SFQ technology. Results show a comparative verification time of Sport lab SFQ logic circuit benchmark suite including 16-bit Array multiplier, 16-bit integer divider and ISCAS'85 circuits with respect to ABC tool for similar CMOS circuits.