QCA Systolic Matrix Multiplier

Abstract

Quantum-dot Cellular Automata (QCA) technology is a promising alternative to CMOS technology. It is attractive due to its fast speed, small area and low power consumption. To explore the characteristics of QCA technology, digital circuit design approaches have been investigated. Due to the inherent wire delay in this technology, QCA appears to be suitable for pipelined architectures particularly. Systolic arrays take advantage of pipelining and parallelism. Therefore, an investigation into systolic array design in QCA technology is provided in this paper. A case study of the first systolic matrix multiplier is designed and analyzed. The results show that by applying the systolic array structure to QCA designs, significant benefits can be achieved particular with large systolic array size, even more so than when applied to CMOS-based technology. QCA has significant advantages in terms of speed and area over CMOS technology, for instance, a factor of 12 smaller in terms of the area in this proposed matrix multiplier design when compared with same CMOS 32 nm implementation.