Abstract
A pulse width modulation (PWM) signal processing circuit based on the concept of A-D merged architecture for implementing intelligence in silicon chips, and to discuss advantages of the circuit through some experimental results. It consists of the PWM core circuit for linear arithmetic units, PWM multiply-and-accumulate circuit, and PWM nonlinear circuit. The number of devices and power dissipation can be reduced drastically comparing with existing binary digital electronics. The proposed circuit is applicable to intelligent processing engines which effectively perform multi-media and neural processings.
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