PWM Control of N-Phase Interleaved Active Front-End Boost Stage-Based Impedance Source Inverter

Abstract

Non-isolated high gain inverters, such as impedance source inverters (ZSI), are suitable for applications with limited input dc source voltage, e.g., microinverters. High gain in these inverters is attributed to the front-end boost stage (FBS). High step-up ratio results in very high input current as the power rating of the inverter goes up. This leads to significant conduction loss in the non ideal elements of the inverter, specifically in the FBS, thereby degrading the efficiency. Paralleling and interleaving the FBS is a feasible solution to achieve higher efficiency. This demands for a generalized pulsewidth modulation (PWM) scheme, which can enable paralleling of multiple interleaved FBSs. In this article, a novel PWM scheme is proposed to implement <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n</i> -phase interleaving of active FBS-based ZSIs. The PWM scheme ensures synchronized operation between the “ <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n</i> ” interleaved FBS and the single inverter stage. As case studies, the PWM scheme is implemented in <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n</i> -phase interleaved current fed switched inverter, switched boost inverter, and quasi switched boost inverter. Steady-state operation of these topologies with three interleaved phases is verified using PLECS simulation. Operation of an interleaved current fed switched inverter with three interleaved phases is verified experimentally using a 200-W proof of concept prototype.