PVMC: Task Mapping and Scheduling under Process Variation Heterogeneity in Mixed-Criticality Systems

Abstract

Embedded systems have migrated from special-purpose hardware to commodity hardware. These systems have also tended to Mixed-Criticality (MC) implementations, executing applications of different criticalities upon a shared platform. Multi-core processors, which are commonly used to design MC systems, bring out new challenges due to the process variations. Power and frequency asymmetry affects the predictability of embedded systems. In this work, variation-aware techniques are explored to not only improve the reliability of MC systems, but also aid the scheduling and energy saving of them. We leverage the core-to-core (C2C) variations to protect high-criticality tasks and provide full service for a high percentage of low-criticality tasks. We formulate a constrained Integer Linear Program (ILP) and propose an optimization heuristic for task mapping and scheduling under Process Variation in Mixed-Criticality systems (PVMC). Our proposed techniques also guarantee timing, reliability, and Thermal Design Power (TDP) constraints by considering the impact of task mapping in variation-affected platforms on system reliability and peak power consumption. Experiments demonstrate that our ILP framework and PVMC algorithm can greatly improve the schedulability and the overall Quality-of-Service (QoS), and provide energy saving up to 27.1% under different quantities of process variation compared with a state-of-the-art algorithm.