PVHArray: An Energy-Efficient Reconfigurable Cryptographic Logic Array With Intelligent Mapping

Abstract

This article presents a coarse-grained reconfigurable cryptographic logic array named PVHArray and an intelligent mapping algorithm for cryptographic algorithms. We propose three techniques to improve energy efficiency without affecting performance. First, the coarse-grained pipeline variable reconfigurable operation units balance the system critical path delay and number of algorithm operations to ensure the best performance. Second, the hierarchical interconnect network overcomes the shortcomings of a single network, providing PVHArray with good interconnectivity and scalability while managing the network hardware resource overhead. Third, the distributed control network supports accurate period-oriented control with a lightweight hardware structure, preserving hardware resources for other performance enhancements. We combine these advances with deep learning to propose a type of smart ant colony optimization mapping algorithm to improve algorithm mapping performance. We implemented our PVHArray on a 12.25 mm2 silicon square with 55-nm CMOS technology, with each algorithm working at its optimum frequency. Experiments show that PVHArray improved performance by about 12.9% per unit area and 13.9% per unit power compared with the reconfigurable cryptographic logic array REMUS_LPP and other state-of-the-art cryptographic structures. For cryptographic algorithm mapping, our smart ant colony optimization (SACO) algorithm reduced compilation time by nearly 38%. Finally, PVHArray supports a variety of types of cryptographic algorithms.