Pulsed-latch-based clock tree migration for dynamic power reduction

Abstract

Minimizing the clock tree has been known as an effective approach to reduce power dissipation in modern circuit designs. However, most existing power-aware clock tree synthesis algorithms still focus on optimizing power in flip-flops, which might have limited power savings. In this work, we explore the pulsed-latch utilization in clock tree synthesis for further power savings. We are the first work in the literature to propose a novel synthesis algorithm to efficiently migrate a flip-flop-based clock tree into a pulsed-latch one. To maintain performance of a clock tree while considering load balance (skew issues) simultaneously, we determine the clock tree topology by the minimum-cost maximum-flow network. Experimental results show that our algorithm can further reduce power consumption by 22% on average compared to approaches without pulsed latches. Categories and Subject Descriptors: B.7.2 [Integrated Circuits]: Design Aids General Terms: Algorithms, Design