Pulsed thermal characterization of a reverse biased pn-junction for ESD HBM simulation

Abstract

Compact electro-thermal simulation of an ESD event in a semiconductor structure requires proper definition and calibration of the equivalent thermal circuit. We demonstrate an approach to determine the device temperature during square pulse stress on the basis of the temperature dependence of the avalanche breakdown voltage. This global temperature is relevant to the transient IV-characteristic. The simulation accuracy of an HBM-stressed diode is improved significantly.