Abstract

Current generation of computing platforms is embracing multi-core and many-core processors to improve the overall performance of the system, meeting at the same time the stringent energy budgets requested by the market. Parallel programming languages are nowadays paramount to extracting the tremendous potential offered by these platforms: parallel computing is no longer a niche in the high performance computing (HPC) field, but an essential ingredient in all domains of computer science. The advent of next-generation many-core embedded platforms has the chance of intercepting a converging need for predictable high-performance coming from both the High-Performance Computing (HPC) and Embedded Computing (EC) domains. On one side, new kinds of HPC applications are being required by markets needing huge amounts of information to be processed within a bounded amount of time. On the other side, EC systems are increasingly concerned with providing higher performance in real-time, challenging the performance capabilities of current architectures. This converging demand raises the problem about how to guarantee timing requirements in presence of parallel execution.The paper presents how the time-criticality and parallelisation challenges are addressed by merging techniques coming from both HPC and EC domains, and provides an overview of the proposed framework to achieve these objectives.

Highlights

  • High-performance computing (HPC) and embedded computing (EC) systems have been traditionally running in opposite directions

  • New high-performance applications are being required by markets needing huge amounts of information to be processed within a bounded amount of time, and embedded systems are increasingly concerned with providing higher performance in real-time, challenging the performance capabilities of current architectures

  • Meeting this dual challenge can only be provided by next-generation many-core embedded platforms, guaranteeing that real-time high-performance applications can be executed on efficient and powerful heterogeneous architectures integrating general-purpose processors with many-core computing fabrics

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Summary

Introduction

High-performance computing (HPC) and embedded computing (EC) systems have been traditionally running in opposite directions. New types of applications are challenging the performance capabilities of hardware platforms, and the demand for increased computational performance is even more challenging when large amounts of data from multiple data sources must be processed and aggregated with guaranteed processing response times This is the case of real-time complex event processing (CEP) systems [33], a new area for HPC in which the data coming from multiple event streams is correlated in order to extract and provide meaningful information within a bounded amount of time. It is essential to guarantee the timing predictability of the performed computations, meaning that arguments and analysis are needed to be able to make arguments of correctness – e.g., performing the required computations within well-specified bounds In this current trend, challenges that were previously specific to each computing domain, start to be common to both domains (including energy-efficiency, parallelisation, compilation, software programming) and are magnified by the ubiquity of many-cores and heterogeneity across the whole computing spectrum.

The predictability challenge
P-SOCRATES approach
Real-time parallel programming model
Tackling the predictability challenge
Application architecture
Overview of the P-SOCRATES stack
Overview of the many-core architecture
Software stack
Related work
Conclusions
Full Text
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