Psi: A Silicon Compiler for Very Fast Protocol Processing

Abstract

Conventional protocols implementations typically fall short, by a few orders of magnitude, of supporting the speeds afforded by high-speed optical transmission media. This protocol processing bottleneck is a key hurdle in taking advantage of the opportunities presented by high-speed communications. This paper describes PSi, a silicon compiler that transforms formal protocol specifications into efficient VLSI implementations. PSi takes advantage of the parallelisms intrinsic to a given protocol to accomplish very high-speed implementations. Initial application of PSi to the IEEE 802.2 (logical link control) lead to processing rates in the order of 106 packets per second (pIs). The 802.2 was selected as a benchmark of complexity; light-weight protocols can accomplish even higher processing rates, reaching the limits set by chip clock rates (i.e., a packet per cycle). These speeds significantly exceed typical of software implementations (up to a few hundreds pIs) or special hardware-assisted implementations (up to a few thousands pIs). More importantly, at these rates when the packet size is 103-4 bits the protocol thruput of 109-10 bitslsec reaches the limiting thruput afforded by memory technology. Thus, the protocol processing bottleneck is pushed to the ultimate bounds set by VLSI technologies. 1. BACKGROUND: THE PROTOCOL PROCESSING BOTTLENECK The rapid advent of optical communication technologies resulted in a significant increase of the speeds at which data may be transmitted. Data transmission rates in the ord~r of 108-109 bits per second (b/s) are becoming a commercial reality while speeds of 109-12 bls are explored at various research labs. This increase in transmission rates reverses the traditional relations among proces~ing and communications technologies. In fact, a bandwidth in the order 109 1 U bls is the current limit of very high-speed processor-memory communications. Therefore, the transmission rates afforded by optical communication technology meet or exceed the rates afforded by processing technologies. Unfortunately, in between the network transmission layer, where bits are communicated, and the processor-memory bus, over which these bits are processed, a collection of protocol layers regulate the flow of these bits. These protocol layers are processed at speeds significantly slower than those supported at the transmission and processing levels. Protocol processing speeds thus present a significant bottleneck in utilizing the speeds afforded by optical transmission technologies to accomplish significantly new applications. Why is protOCOl processing slow? How can we improve protocol design to support high speed communications? How can we improve protocol implementations to accomplish orders of magnitude speed increase? These questions attracted significant interest recently [1-7]. Figure 1, below, depicts the typical processing tasks associated with a protocol (center rectangle) and the data that they use (surrounding rectangles). t Columbia University, Computer Science Dep:rrtment, NY, NY. * Work supported in pan by DARPA contract #F-2960I-87-C-0074