Pseudorandom built-in self-test methodology and implementation for the IBM RISC System/6000 processor

Abstract

This paper describes a unified self-test and system bring-up methodology. The components involved include a common on-chip processor (COP) that executes the chip self-test sequence and provides an interface to the COP bus, a serial bus (COP bus) that links the chips to OCS and ESP, an on-card sequencer (OCS) that controls the self-test and system initialization sequences, and an engineering support processor (ESP) that is used for system verification, bring-up, and debug. Almost all RISC System/6000* chips contain embedded RAMs such as register files, caches, and directories; therefore, the self-test methodology described here is particularly suitable for logic chips that contain embedded arrays. Logic and RAM self-test is executed by a control processor (COP) integrated on the chips. The COP controls the self-test sequence, generates pseudorandom test vectors, scans them into chip registers, and provides the select lines that establish a one-to-one correspondence between RAM input/output and chip registers. The COP also drives RAM read/write lines during self-test, scans the captured RAM outputs, and compresses them to obtain a signature. After the vectors are scanned in, the chip runs for one or two system cycles, the logic outputs are captured in registers, and the chip state is scanned back into the COP, where it is compressed to obtain a signature. This procedure is repeated many times, and the final signature is then compared with a predetermined “good” signature to establish whether the chip is good or bad. Special techniques are developed to improve the coverage of logic that feeds RAMS or receives its inputs from RAMs. Both ac and dc self-test are described. The self-test sequence is controlled by a program stored in the OCS, and ESP is used during system bring-up to set up break-points and to display and modify the machine state.