Prototype Thermal Design for a 256 Pixel Transition Edge Sensor Bolometer Array with Additional on-chip Cooling

Abstract

Normal‐metal/insulator/superconductor (NIS) tunnel junctions can be integrated with transition edge sensor (TES) bolometers to provide additional cooling to the sensor. For example, a TES array cooled to 300 mK by a 3He refrigerator could be enhanced with additional on‐chip NIS cooling to decrease the effective bath temperature of each TES to 100 mK. The noise of the array with on‐chip cooling would be ∼40% lower than that of a similar array without on‐chip cooling. Additionally, the lower bath temperature allows a more physically robust design with the same saturation power per pixel. However, on‐chip NIS cooling does not come for free. While the NIS coolers reduce the bath temperature seen by each pixel, they also dissipate about 100 times as much power as the pixel alone and increase the fabrication complexity. We describe a potential thermal design of a 256 pixel TES bolometer array with on‐chip cooling. We show that such an array is feasible despite the increase in power dissipation.