Protograph QC-LDPC and Rate-Adaptive Polar Codes Design for MLC NAND Flash Memories

Abstract

A protograph-based quasi-cyclic (QC) low-density parity-check (LDPC) code for multi-level cell (MLC) NAND flash memories is proposed in this paper. In this design approach, the quantized voltage signals are measured for soft decoding because the exact voltage values are unavailable. Flash memory channels are asymmetric, and therefore, not optimal for existing LDPC codes optimized for symmetric additive white Gaussian noise (AWGN)-like channels. Mutual information (MI) between the input and output of flash memory is used to model the quantized log-likelihood ratio (LLR) messages. The base matrix of the method is constructed according to the degree sequences optimized by the modified extrinsic information transfer (EXIT) chart method for flash memories. The designed protograph-based codes have a low-complexity QC encoder structure with a readily parallelizable decoder structure. In addition, rate-adaptive polar code design based on Bhattacharyya parameters of the memory cell bits is proposed to further improve the storage efficiency of the MLC NAND flash memories. The code design takes advantage of the inherent characteristics of MLC flash memory channel to iteratively calculate the Bhattacharyya parameter of each memory cell bit, where the punctured positions are selected by choosing the bits with higher Bhattacharyya parameters to construct rate-adaptive polar codes. The simulation results confirm the benefits of the proposed coding schemes.