Abstract
Simultaneous reachability analysis is a relief strategy for validating protocols specified as a collection of n ( n ≥ 2) processes communicating over error-free simplex channels. This analysis is based on the execution of sets of simultaneously executable transitions at every simultaneously reachable global state of a given protocol. It is proven that simultaneous reachability analysis identifies every deadlock, every nonexecutable transition, every missing receiving transition causing an unspecified reception and every channel at which a buffer overflow occurs. An empirical study is carried out to demonstrate the efficiency of simultaneous reachability analysis in terms of time and memory requirements. In this study, 300 protocols, constructed by an automatic protocol synthesizer, are used and results are evaluated with respect to the characteristics of these protocols. The results of applying the proposed strategy on two real protocols are given.
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