Abstract
The Proteus architecture is a highly parallel MIMD, multiple instruction multiple data, machine optimized for large granularity tasks such as machine vision and image processing. The system can achieve 20 G-flops (80 G-flops peak). It accepts data via multiple serial links at a rate of up to 640 megabytes/second. The system employs hierarchical reconfigurable interconnection network with the highest level being a circuit switched enhanced hypercube serial interconnection network for internal data transfers. The system is designed to use 256 to 1.024 risc processors. The processors use 1 M byte external read/write allocating caches for reduced multiprocessor contention. The system detects, locates and replaces faulty subsystems using redundant hardware to facilitate fault tolerance. The parallelism is directly controllable trough an advanced software system for partitioning, scheduling and development.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
Sign-in/Register to access full text options 
Free) 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a call
