Abstract
The decreasing size of the transistor has increased the vulnerability towards faults. Increasing number of cores on a single chip has made the concept of Network on Chip (NoC) a standard communication backbone among cores. This facility comes with vulnerability of faults in the system due to decreasing size of transistors. A permanent fault in the network leads to undesirable consequence such as permanent blocking of flits or failure of the whole router. Preserving the router in the operational state has a significant impact on the reliability of the system. Permanent fault in buffers and pipeline stages of the router has a high impact on performance. The proposed router architecture Protector provides faults protection to both buffers and pipelines stages by exploiting the concepts of borrowing from other resources, using bypass paths and by creating multiple paths to reach output. The proposed router incurred an area overhead of 30% as compared to the baseline design. Reliability analysis using Silicon Protection Factor indicates that the proposed router has better fault tolerance efficiency as compared to state of the art. Latency analysis using PARSEC and SPLASH-2 benchmarks indicates proposed router incurs 13% and 16% latency overhead in the presence of faults.
Highlights
Miniscule technology feature sizes into the deep nanometer regime have enabled microprocessors with billions of transistors on a single chip [1,2]
Higher the value of SPF means that design has high fault tolerance towards permanent faults
The permanent faults in the pipeline stages are not tackled which will results in failure of the router if permanent fault manifests in the router pipelines
Summary
Miniscule technology feature sizes into the deep nanometer regime have enabled microprocessors with billions of transistors on a single chip [1,2]. A single fault in a NoC creates errors in the chip which results in undesirable conditions, i.e. increased latencies, packet loss and degraded performance. A fault tolerant router architecture is presented to tolerate permanent faults occurring at various locations in the router and affecting the reliability of the chip. This architecture provides fault tolerance and enhances the performance of the network by a grouping of adjacent ports, sharing of resources, temporal parallelism, rectification circuitry and multiple routes to avoid faults.
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