Protecting On-Chip Data Access Against Timing-Based Side-Channel Attacks on Multicores

Abstract

Shared hardware resources in multicore processors enable massive performance gains but bring security challenges. Adversaries have successfully leaked on-chip data using timing-based side-channel attacks (SCA) targeting shared caches, network-on-chip, and memory controller hardware. Existing mitigation schemes protect on-chip data against attacks targeting a single hardware resource, while leaving the additional channels unprotected. This paper implements multi-level mitigation schemes that protect on-chip data access against timing-based SCA targeting multiple shared hardware resources. It evaluates the performance implications of individual and multi-level mitigation schemes using security-critical graph and machine learning workloads. The multi-level mitigation schemes are shown to have ~2% overall performance implication that primarily depends on the cache behavior of the workloads.