Protecting IP core during architectural synthesis using HLT‐based obfuscation

Abstract

For protecting an intellectual property (IP) core, it must be harder to reverse engineer. Structural obfuscation can play an important role in achieving this goal. A novel structural obfuscation methodology during architectural synthesis using multiple compiler-based high-level transformations (HLTs) that yield functionally equivalent designs (data flow graphs) which are camouflaged in identity is proposed. The proposed obfuscation methodology is driven through a number of HLT techniques such as redundant operation elimination, logic transformation and tree height transformation. In addition to performing obfuscation, performing area-delay tradeoff during exploring low-cost obfuscated design is also possible using these HLT techniques in the proposed methodology. Owing to multiple stages of HLT incorporated in the proposed approach during obfuscation, it yields a highly robust design which on integration with particle swarm optimisation-based exploration framework produced low-cost obfuscated IP designs. Results of the proposed approach yielded an enhancement in strength of obfuscation of 20.19% and reduction in obfuscated design cost of 59.66% compared with a similar approach.