Prospective Incorporation of Booster in Carbon Interconnects for High-Speed Integrated Circuits

Abstract

VLSI technology has eulogistically grown over the years. This has been made feasible due to continuous scaling of technology. Miniaturization of technology and conscientious demand of high-speed applications have resulted in dense and compact packaging of on-chip interconnects and devices. Copper has been widely used as an on-chip interconnect material in VLSI chips. However, copper is constrained by the grain and surface boundary scattering effects at scaled technology nodes that limit its utility and further incorporation in futuristic integrated circuit (IC) designs. Subsequently, carbon-based on-chip interconnects have been investigated and proven to be one of the effective alternatives to conventional copper interconnects. The present work vividly explores and investigates carbon nano-materials that can be used for high-speed VLSI interconnects. The other important entanglement with on-chip interconnect is that its parasitic increases and henceforth output performance degrades as the length of wiring over IC increases. This can be eminently alleviated using prospective booster insertion in between on-chip interconnects. The elegant booster insertion technique for prosperous carbon interconnects has been marginally explored till date and henceforth taken up in this work. This paper meticulously investigates various system characteristics such as delay, power dissipation, crosstalk, signal integrity, eye diagram for different interconnect materials such as copper, carbon-based CNTs and GNRs. It is observed that carbon interconnects impressively outperform in terms of delay, power, crosstalk and high-speed operation than conventional copper interconnects.