Abstract

In this letter, we discuss how to prepare millions of uniform p-type silicon (Si) microparticles using top-down fabrication processes and how to remotely control their dynamics when they are suspended in water and powered by external alternating current (AC) electric fields. These microparticles present positively charged carrier types (majority carriers from boron atom doping in the intrinsic Si) and negatively charged carrier types (minority carriers from the free electrons in the Si lattice), which electrostatically affects their negatively charged surfaces and enables a variety of programmable behaviors, such as directional assembly and propulsion. At high AC electric field frequencies ( f > 10 kHz), the microparticles assemble by attractive dielectrophoretic polarization forces. At low electric field frequencies ( f ≤ 10 kHz), the microparticles propel by induced-charge electrophoretic flows. The ability to manipulate the electrostatic potential distribution within and around the microparticles (i.e., by controlling electronic carrier types through doping) is useful for designing a number of new dynamic systems and devices with precise control over their behaviors.

Highlights

  • Advances in integrated circuit fabrication have enabled the routine generation of millions of well-defined semiconductor devices with sophisticated designs in a single run

  • The ability to engineer the geometric shape, doping profile, and surface characteristics enables the construction of semiconductor devices with broad degrees of complexity; these devices can be manufactured as small as a few nanometers to as large as several millimeters.[1,2]

  • The SOI wafers were comprised of a p-type Si handle substrate (270 μm thick, borondoped) with a silicon dioxide layer (SiO2; 2 μm thick, referred to as a buried oxide, or BOX layer) that was bonded to a single crystal p-type Si device layer (4 μm thick, boron-doped)

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Summary

Introduction

Advances in integrated circuit fabrication have enabled the routine generation of millions of well-defined semiconductor devices with sophisticated designs in a single run. (Received 27 August 2018; accepted 19 November 2018; published online 7 December 2018)

Results
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