Proposal of Global Strain Clocking Scheme for Majority Logic Gate

Yabo Chen,Bo Wei,Mingxu Song,Xiaokuo Yang,Huanqing Cui

doi:10.1109/access.2020.2989930

Abstract

A stairs-type global strain clocking mechanism for nanomagnetic majority logic gate based on shape engineering of nanomagnets was designed in this paper. Reasonable size nanomagnets and proper strain clocking scheme ensure the computing architecture pipelined at room temperature. The optimal global strain clocking scheme was obtained by investigating the impact of magnetic layer thickness and width on clocking period and strain magnitude. Encouragingly, for the global strain clocking, information transmission speed of majority logic gate is increased 1-2 times as against the local strain clocking scheme due to decreasing the number of start-ups during information transmission. While the energy dissipated per clock cycle of the global strain clocking scheme consumes 3-4 times less energy than that of local strain clocking scheme. Moreover, global clocking is used to control a nanomagnetic logic device(NMLD), in which case single device consisted of many nanomagnets can be treated as single nanomagnet. However, magnetization switching is error-prone in the presence of thermal noise at room temperature. Therefore, the proper structure parameters of the device are obtained at room temperature, in which case the error probability of the majority logic gate is 0.5% in theoretical simulation. These results provide essential guidance for the design of energy-efficient multiferroic nanomagnetic logic devices.

Highlights

With the dimensions of CMOS devices further scaling, the problems of quantum tunneling effect and power consumption have become stumbling block to improving integration [1]
The optimal global strain clocking scheme was obtained by studying information propagation of this majority logic gate at the room temperature
Compared with the traditional clocking scheme, the global strain clocking consumes less energy to perform majority computing and significantly improves the operation frequency of the majority logic gate

Summary

Introduction

With the dimensions of CMOS devices further scaling, the problems of quantum tunneling effect and power consumption have become stumbling block to improving integration [1]. Crocker et al constructed majority logic gates by using external driven nanomagnets and magnetic field clocking [21]. Zhang et al designed the majority logic gates that was composed of three trapezoid nanomagnets with different aspect ratios and two rectangular nanomagnets, which adopted bidirectional magnetic fields as clocking scheme [22], [23].

Results

Conclusion