Abstract
A novel silicon-on-insulator (SOI) polarization splitter-rotator (PSR) with a large fabrication tolerance is proposed based on cascaded multimode interference (MMI) couplers and an assisted mode-evolution taper. The tapers are designed to adiabatically convert the input TM(0) mode into the TE(1) mode, which will output as the TE(0) mode after processed by the subsequent MMI mode converter, 90-degree phase shifter (PS) and MMI 3 dB coupler. The numerical simulation results show that the proposed device has a < 0.5 dB insertion loss with < -17 dB crosstalk in C optical communication band. Fabrication tolerance analysis is also performed with respect to the deviations of MMI coupler width, PS width, slab height and upper-cladding refractive index, showing that this device could work well even when affected by considerable fabrication errors. With such a robust performance with a large bandwidth, this device offers potential applications for CMOS-compatible polarization diversity, especially in the booming 100 Gb/s coherent optical communications based on silicon photonics technology.
Highlights
Silicon photonics, which takes advantages of the mature complementary metal oxide semiconductor (CMOS) process and strong optical confinement in the SOI waveguide, has been considered to be one of the most promising candidates of the next-generation photonics market for many applications, including the optical communications, optical interconnects and high-performance computers (HPCs) [1]
Systems [7, 8], but it would be difficult to achieve the tradeoff between polarization insensitivity and good performance especially for the thin SOI wafers with 220 nm top silicon thickness which are preferred by the silicon photonic foundries [9]
We believe that these remarkable tolerances will significantly improve the manufacturing yield, which is advantageous to achieve high-density silicon photonic circuits with more complex functionalities
Summary
Silicon photonics, which takes advantages of the mature complementary metal oxide semiconductor (CMOS) process and strong optical confinement in the SOI waveguide, has been considered to be one of the most promising candidates of the next-generation photonics market for many applications, including the optical communications, optical interconnects and high-performance computers (HPCs) [1]. Tremendous efforts have been done towards polarization-insensitive structures for specific applications in different material systems [7, 8], but it would be difficult to achieve the tradeoff between polarization insensitivity and good performance especially for the thin SOI wafers with 220 nm top silicon thickness which are preferred by the silicon photonic foundries [9] Another promising approach which may be more suitable for SOI photonics platform is the polarization diversity scheme [10]. We further analyze the fabrication tolerance of this device, showing that the performance is very robust even for large fabrication deviations in terms of etch depth, MMI width, PS width and refractive index of the upper-cladding This PSR could be fabricated in a standard CMOS process and integrated with other functional components to realize a more complex function in the coherent optical communications beyond 100 Gb/s
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