Proposal and Realization of Vertical GaN Nanowire Static Induction Transistor

Abstract

Vertical gallium nitride (GaN) nanowire static induction transistors (SITs) are proposed and realized for micro display for the first time. A top-down dry etch was employed to form the GaN nanowires with height of ~1.5 μm and diameter of ~350 nm, followed by the SIT fabrication with the gate-all-around design which benefits are better gate control, combined with reduced surface area consumption for improved scaling and integration. Relatively low voltages are required for controlling the vertical current from source to drain. The I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</sub> to I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">off</sub> ratio is measured as 2 × 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">6</sup> , which is ~900 times larger than the previous reported GaN fin SIT. These results demonstrated that vertical nanowire SITs by the use of undoped GaN which is typically the template layer for light-emitting diodes (LEDs) will enable voltage-controlled components for new integration schemes and opportunities in micro display technology.