Property verification of asynchronous systems

Abstract

We demonstrate a new modelling technique that facilitates the description and the formal verification of timing properties of concurrent systems, such as asynchronous digital hardware. We utilise a process algebra and its associated automatic verification system and construct models and verification strategies using them. Utilising the hierarchical nature of our approach, these techniques may then be applied to larger systems, such as asynchronous circuits of commercial complexity. The modelling techniques introduced permit four distinct classes of objects, namely system components, assumed constraints on their behaviour, properties requiring proof and behaviour refinements, all to be modelled by a process. We illustrate this approach by modelling the necessary timing relationships required for the correct operation of asynchronous micropipline stages and then verifying that the resulting behaviour is correct. Finally, we demonstrate how the same models are used to make some observations about the performance and the timing properties of such designs.